1 ps8478 04/27/00 product features ? zero input-output propagation delay ? less than 200ps input to output propagation delay ? multiple low-skew outputs C output-output skew less than 250ps C device-device skew less than 700ps C two banks of four outputs and one on-chip C internal feedback connection ? 10 mhz to 100 mhz operating range ? low jitter <200ps ? 3.3v operation ? high drive option (pi6c2309-1h) ? temperature rating: commercial & industrial ? space-saving 16-pin, 150-mil soic package (w16) and 16-pin tssop package (l16) functional description providing two banks of four outputs, the pi6c2309-1 is a 3.3v zero- delay buffer designed to distribute clock signals in applications including pc, workstation, datacom, telecom, and high-performance systems. the pi6c2309-1 provides 9 copies of a clock signal that has less than 200ps propagation delay compared to the reference clock. the skew among the output clock signals for pi6c2309-1 is less than 250ps. when there are no rising edges on the ref input, the pi6c2309-1 enters a power-down state. in this mode, the pll is off and all outputs are three-stated. this results in less than 50 m a of current draw. the pi6c2309-1 has two banks of four outputs and a clk_out that can be controlled by the select inputs (see table below). if all output clocks are not required, bank b can be three-stated. for test purposes or if the internal pll is not needed, it can be bypassed. block diagrams pin configuration pi6c2309-1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 3.3v zero-delay buffer pi6c2309-1 2 s1 s] 4 - 1 [ a k l c] 4 - 1 [ b k l ct u o _ k l ce c r u o s t u p t u on w o d t u h s l l p 00 e t a t s - e e r h te t a t s - e e r h tn e v i r dl l pn 01 n e v i r de t a t s - e e r h tn e v i r dl l pn 10 n e v i r dn e v i r dn e v i r de c n e r e f e ry 11 n e v i r dn e v i r dn e v i r dl l pn select input decoding for pi6c2309-1 1 2 3 v dd 4 gnd 5 clka2 6 clkb2 7 s1 8 clkb1 clk_out clka3 v dd clkb4 clkb3 s2 16 15 14 13 12 11 10 9 ref clka1 gnd clka4 16-pin l, w pll mux ref fbk s2 s1 select input decoding clk_out clka1 clka2 clka3 clka4 clkb2 clkb3 clkb4 clkb1
2 ps8478 04/27/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2309-1 3.3v zero-delay buffer to achieve a zero delay between the input and output, all outputs should be uniformly loaded. the relative loading of clk_out(with respect to the remaining outputs) can adjust the input-output delay. this is shown in the graph above. zero delay and skew control ref. input to clka/clkb delay vs. difference in loading between clk_out pin and clka/clkb pins. maximum ratings supply voltage to ground ................................ C0.5v to +7.0v dc input voltage (except ref) ................ C0.5v to v dd +0.5v dc input voltage ref ............................................... C0.5 to 7v storage temperature ...................................... C65o c to +150oc maximum soldering temperature (10 seconds) ............... 260oc junction temperature ...................................................... 150oc static discharge voltage (per mil-std-883, method 3015) ................................. >2000v for applications requiring zero input-output delay, all outputs, including clk_out, should be equally loaded. even if clk_out is not used, it must have a capacitive load that is equal to that on every other output. if input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. 600 800 400 200 0 -200 -400 -600 -800 -900 -1000 -25 -20 -15 -10 -5 0 5 10 15 20 25 output load difference: clk_out load - clka/clkb load (pf) ref - input to output clk delay (ps) pi6c2309-1h pi6c2309-1
3 ps8478 04/27/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2309-1 3.3v zero-delay buffer electrical characteristics (over the operating condition) r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t s e t. n i m. x a ms t i n u v l i e g a t l o v w o l t u p n i ) 4 ( ?? 8 . 0 v v h i e g a t l o v h g i h t u p n i ) 4 ( ? 0 . 2 ? i l i t n e r r u c w o l t u p n iv n i =v 0 ? 0 5 m a i h i t n e r r u c h g i h t u p n iv n i =v d d ? 0 0 2 v l o e g a t l o v w o l t u p t u o ) 5 ( i l o a m 8 = i l o ) h 1 - ( a m 2 1 = ? 4 . 0 v v h o e g a t l o v h g i h t u p t u o ) 5 ( i h o a m 8 C = i h o ) h 1 C ( a m 2 1 C = 4 . 2 ? i d d ) e d o m d p (t n e r r u c y l p p u s n w o d r e w o p0 = 1 s , 1 = 2 s , z h m 0 = f e r ? 0 5 m a i d d t n e r r u c y l p p u s , z h m 6 6 . 6 6 , s t u p t u o d e d a o l n u v t a s t u p n i t c e l e s d d d n g r o ? 0 5a m pin description n i pl a n g i sn o i t p i r c s e d 1f e r ) 1 ( , t u p n i t n a r e l o t v 5 , y c n e u q e r f e c n e r e f e r t u p n i t u p n i k c o l c m u r t c e p s d a e r p s s w o l l a 21 a k l c ) 2 ( a k n a b , t u p t u o k c o l c 32 a k l c ) 2 ( a k n a b , t u p t u o k c o l c 4v d d y l p p u s v 3 . 3 5d n gd n u o r g 61 b k l c ) 2 ( b k n a b , t u p t u o k c o l c 72 b k l c ) 2 ( b k n a b , t u p t u o k c o l c 82 s ) 3 ( 2 t i b , t u p n i t c e l e s 91 s ) 3 ( 1 t i b , t u p n i t c e l e s 0 13 b k l c ) 2 ( b k n a b , t u p t u o k c o l c 1 14 b k l c ) 2 ( b k n a b , t u p t u o k c o l c 2 1d n gd n u o r g 3 1v d d y l p p u s , v 3 . 3 4 13 a k l c ) 2 ( a k n a b , t u p t u o k c o l c 5 14 a k l c ) 2 ( a k n a b , t u p t u o k c o l c 6 1t u o _ k l c ) 2 ( n i p s i h t n o k c a b d e e f l a n r e t n i , t u p t u o k c o l c operating conditions notes: 1. weak pull-down. 2. weak pull-down on all outputs. 3. weak pull-ups on these inputs. 4. ref and clk_out inputs have a threshhold voltage of v dd /2. 5. parameter is guaranteed by design and characterization. not 100% tested in production. r e t e m a r a pn o i t p i r c s e d. n i m. x a ms t i n u v d d e g a t l o v y l p p u s0 . 36 . 3v t a ) h 1 - 9 0 3 2 , 1 - 9 0 3 2 ( e r u t a r e p m e t l a i c r e m m o c ) t n e i b m a ( 00 7 c o t a ) i h 1 - 9 0 3 2 , i 1 - 9 0 3 2 () t n e i b m a ( e r u t a r e p m e t l a i r t s u d n i0 4 C5 8 c l e c n a t i c a p a c d a o l ? 0 3 f p c n i e c n a t i c a p a c t u p n i ? 7
4 ps8478 04/27/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2309-1 3.3v zero-delay buffer notes: 5. parameter is guaranteed by design and characterization. not 100% tested in production. 6. for definition of t 1-8 , see switching waveforms on page 5 switching characteristics (5,6) (over the operating condition) s r e t e m a r a pe m a ns n o i t i d n o c t s e t. n i m. p y t. x a ms t i n u f k l c y c n e u q e r f t u p t u od a o l f p 0 30 10 0 1z h m e l c y c y t u d ) 5 ( t = 2 ? t 1 v t a d e r u s a e m d d , 2 / f out z h m 6 6 . 6 6 < 5 40 55 5 % e l c y c y t u d ) 5 ( t = 2 ? t 1 f , v 4 . 1 t a d e r u s a e m t u o z h m 6 . 6 6 =0 40 50 6 t 3 e m i t e s i r ) 5 ( f p 0 3 @ n e e w t e b d e r u s a e m v 0 . 2 d n a v 8 . 0 5 . 2 s n t 3 e m i t e s i r ) 5 ( f p 5 1 @ 5 . 1 t 3 e m i t e s i r ) 5 ( ) h 1 - ( f p 0 3 @ 5 . 1 t 4 e m i t l l a f ) 5 ( f p 0 3 @ 5 . 2 t 4 e m i t l l a f ) 5 ( f p 5 1 @ 5 . 1 t 4 e m i t l l a f ) 5 ( ) h 1 - ( f p 0 3 @ 5 . 1 t 5 w e k s t u p t u o o t t u p t u o ) 5 ( d e d a o l y l l a u q e s t u p t u o l l a0 5 2 s p t 6 o t e g d e g n i s i r t u p n i f e r , y a l e d e g d e g n i s i r t u o _ k l c ) 5 ( v t a d e r u s a e m d d 2 /00 5 3 t 7 w e k s e c i v e d o t e c i v e d ) 5 ( v t a d e r u s a e m d d e h t n o 2 / s e c i v e d f o s n i p t u o _ k l c 00 0 7 t 8 e t a r w e l s t u p t u o ) 5 ( n o v 0 . 2 d n a v 8 . 0 n e e w t e b d e r u s a e m 2 # t i u c r i c t s e t g n i s u e c i v e d h 1 C 1s n / v t j r e t t i j e l c y c o t e l c y c ) 5 ( , z h m 7 6 . 6 6 t a d e r u s a e m f p 5 1 @ s t u p t u o d e d a o l 0 0 2s p t k c o l e m i t k c o l l l p ) 5 ( s k c o l c d i l a v , y l p p u s r e w o p e l b a t s t u o _ k l c d n a f e r n o d e t n e s e r p s n i p 0 . 1s m
5 ps8478 04/27/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2309-1 3.3v zero-delay buffer switching waveforms test circuit #1 v dd c load v dd gnd gnd outputs 0.1f 0.1f test circuit for all parameters except t 8 t 2 t 1 1.4v 1.4v 1.4v t 3, t 8 t 4, t 8 0.8v 2.0v 0.8v 2.0v output 0v 3.3v 1.4v t 5 output 1.4v output v dd /2 t 6 input v dd /2 clk_out v dd /2 t 7 clk_out device 1 v dd /2 clk_out device 2 duty cycle timing all outputs rise/fall time output-output skew input-output propagation delay device-device skew
6 ps8478 04/27/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c2309-1 3.3v zero-delay buffer seating plane .050 bsc 1 16 0-8? .149 .157 x.xx x.xx denotes dimensions in millimeters 3.78 3.99 .386 .393 9.80 10.00 1.27 .053 .068 1.35 1.75 .2284 .2440 5.80 6.20 .0040 .0098 0.10 0.25 .013 .020 .0155 .0260 0.330 0.508 0.393 0.660 .0075 .0098 0.25 0.50 .0099 .0196 x 45? 0.19 0.25 .016 .050 0.41 1.27 ref pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com package diagrams 16-pin soic (150-mil wide) w package note: controlling dimensions in millimeters. ref: jedec ms - 012 ac ordering information .193 .201 .047 max. .002 .006 seating plane .0256 bsc .018 .030 .004 .008 .252 bsc 1 16 .169 .177 x.xx x.xx denotes controlling dimensions in millimeters 0.05 0.15 6.4 0.45 0.75 0.09 0.20 4.3 4.5 1.20 4.9 5.1 0.65 0.19 0.30 .007 .012 16-pin tssop l package e d o c g n i r e d r oe m a n e g a k c a pe p y t e g a k c a pe g n a r g n i t a r e p o w 1 - 9 0 3 2 c 6 i p 6 1 wc i o s l i m - 0 5 1 n i p - 6 1 l a i c r e m m o c w h 1 - 9 0 3 2 c 6 i p l 1 - 9 0 3 2 c 6 i p 6 1 lp o s s t m m 4 . 4 n i p - 6 1 l h 1 - 9 0 3 2 c 6 i p i w 1 - 9 0 3 2 c 6 i p 6 1 wc i o s l i m - 0 5 1 n i p - 6 1 l a i r t s u d n i i w h 1 - 9 0 3 2 c 6 i p i l 1 - 9 0 3 2 c 6 i p 6 1 lp o s s t m m 4 . 4 n i p - 6 1 i l h 1 - 9 0 3 2 c 6 i p
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